1. Field of Invention
The present invention relates to a fabrication method for an integrated circuit. More particularly, the present invention relates to a method for lowering the demand in alignment accuracy in an integrated circuit fabrication process.
2. Description of Related Art
Photolithography is one of the most important steps in semiconductor processing. As devices become smaller, the demand in alignment accuracy is higher and the processing window is reduced. In order to have an accurate alignment, a more advanced and usually more costly lithography machine is required.
For example, the fabrication of a conventional mask ROM (Read-Only Memory) device would encounter the aforementioned problem. During the coding of a mask ROM device according to the prior art, as shown in FIG. 1, a pre-coding layer 20 is first formed on a substrate 10. This pre-coding layer 20 comprises a plurality of openings 30 that corresponds to the pre-coding region of the substrate 10. A photoresist layer 40 that comprises the pre-coding opening 50 is formed over the pre-coding layer 20. Using the photoresist layer 40 as a coding mask, an ion coding process is performed. Since forming the opening 50 in the photoresist layer 40, the opening 50 has to align accurately to the pre-coding region in the substrate 100. In the case when a misalignment occurs, as shown in FIG. 1, the opening is excessively misaligned to one side. The pre-coding opening 30 is then not completely exposed. Therefore, during the coding process, only a portion of the dopants are implanted into the coding region and the purpose of coding is thereby not achieved. In the prior art, the alignment accuracy requirement is very high. The processing window is therefore very small. In order to increase the alignment accuracy, a more advanced machine is used for the lithographic process. However, an advanced machine would greatly increase manufacturing cost.
Referring to FIG. 2, in order to obviate the aforementioned problem, one conventional approach is to enlarge the opening 60 of the coding mask 40 in order to completely expose the pre-coding opening 30 in the mask layer 20. However, even the dimension of the opening 60 of the coding mask 40 is increased, extra dopants may be implanted into the undesired coding region. The distance between the neighboring pre-coding openings 30 needs to be increased to prevent such problem. Consequently, the miniaturization of the device can not be effectively achieved.
Accordingly, the present invention provides a method for forming a mask layer, wherein the alignment accuracy requirement in the fabrication of an integrated circuit can be relaxed so as to greatly increase the process window.
The present invention provides a method to relax alignment accuracy requirement in the fabrication of an integrated circuit, wherein the method comprises forming a mask layer over a substrate, and the mask layer is formed with a plurality of first openings. Thereafter, a buffer layer fills the first openings. A photoresist layer is then formed on the substrate, followed by patterning the photoresist layer to form a second opening which exposes a part of the buffer layer. Isotropic etching is further performed to remove the buffer layer exposed by the second opening to expose the sidewall of the corresponding first opening. The photoresist layer is further removed to expose the mask layer that comprises the opening pattern and the embedded buffer layer, wherein the mask layer is served as a hard mask for the subsequent process.
In accordance to the embodiment of the present invention, the mask layer is formed with, for example, silicon oxide, while the buffer layer is formed with, for example, a spin-on material or a metal. To remove the buffer layer exposed by the second opening, an etchant of a high buffer layer-to-mask layer etch selectivity is used. Therefore, even an alignment error occurs when the photoresist layer is defined to form the second opening, the buffer layer in the first opening that corresponds to the second opening is completely removed as long as the second opening exposes a portion of the buffer layer in the corresponding first opening. In other words, as long as the process in defining the first opening in the mask layer is accurate, the alignment accuracy requirement for the second opening can be signficiantly relaxed. When the second opening is formed to expose a portion of the buffer in the corresponding first opening, the first opening is exposed when the buffer layer in the first opening that corresponds to the second opening is completely removed. The mask layer that comprises the opening and the embedded buffer layer can thus serve as a hard mask of the subsequent process.
In accordance to the present invention, the opening in the mask layer is first filled with a buffer layer. Further using a photoresist layer as an etching mask, the buffer layer in a pre-determined region is completely removed based on the different etching rate of the buffer layer and the mask layer. The mask layer that comprises the opening and the embedded buffer layer is then used as a hard mask layer for the subsequent processing.
Since the alignment accuracy requirement for the second opening is relaxed, the process window can be greatly increased according to the present invention.
Since the opening of the mask layer can be accurately aligned with the predetermined region, the consequences resulted from a misalignment of the opening in the mask layer as in the prior art are prevented.
Moreover, the mask layer that comprises the opening, and the embedded buffer layer are together used as a hard mask in the subsequent manufacturing process. The alignment accuracy of the hard mask layer is completely determined by the accuracy in the patterning process of the mask layer and will not be affected by any alignment error occurs during the patterning of the photoresist layer for the second opening.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.